The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a vertical transport field effect transistor which includes an abrupt junction that is located at an interface of a bottom source/drain extension region and sidewall surfaces of a lower portion of a semiconductor fin, as well as a method of forming such a structure.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar (or fin) defines the channel with the source and drain located at opposing ends of the semiconductor pillar. Vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
One potential drawback with conventional vertical transistors is that there is a difficulty in providing a bottom source/drain structure that contains an abrupt junction profile. Notably, and in some conventional processes of providing a bottom source/drain structure, a high thermal budget (on the order of 800° C. or greater) is required to drive-in dopants from the bottom source/drain structure into a semiconductor material portion that is adjoined to a semiconductor fin to form the bottom extension regions. Such a high thermal budget provides a broad dopant profile. There is thus a need for providing a vertical transistor structure which includes an abrupt junction that is located at an interface of a bottom source/drain extension region and sidewall surfaces of a lower portion of a semiconductor fin.